Numerical Simulation of Transient Response in 3-D Multi-Channel Nanowire MOSFETs Submitted to Heavy Ion Irradiation

The bulk MOSFET scaling has recently encountered significant limitations, mainly related to the gate oxide (SiO2) leakage currents (Gusev et al., 2006; Taur et al., 1997), the large increase of parasitic short channel effects and the dramatic mobility reduction (Fischetti & Laux, 2001) due to highly doped Silicon substrates precisely used to reduce these short channel effects. Technological solutions have been proposed in order to continue to use the “bulk solution” until the 32 nm ITRS node (ITRS, 2009). Most of these solutions envisage the introduction of high-permittivity gate dielectric stacks (to reduce the gate leakage, (Gusev et al., 2006; Houssa, 2004), midgap metal gate (to suppress the Silicon gate polydepletioninduced parasitic capacitances) and strained Silicon channel (to increase carrier mobility (Rim et al., 1998). However, in parallel to these efforts, alternative solutions to replace the conventional bulk MOSFET architecture have been proposed and studied in the recent literature. One solution is the radical change of the device architecture such as in MultipleGate devices introducing additional gate electrodes: 2 (double-gate), 3 (FinFET or trigate) or 4 (gate-all-around, completely surrounding the channel). Silicon nanowires MOSFETs with gate-all-around (GAA) provide an original and very promising architecture to further increase the integration density and performances of nano-devices (Park & Colinge, 2002). These structures exhibit a superior control of short channel effects resulting from an exceptional electrostatic coupling between the conduction channel and the surrounding gate electrode. As a result, intrinsic channels can be used leading to higher mobilities and drain currents. 3D Multi-Channel MOSFETs (MCFETs) have been recently proposed to achieve a higher current drivability and a significant enhancement of the on-state current over the off-state current ratio (ION/IOFF) (Bernard et al., 2007; Ernst et al., 2006) compared to conventional single channel devices. MCFETs combine the advantages of excellent control of shortchannel effects with a high on-state current due to a multiple-gate architecture and the 3-D integration of vertically stacked channels. GAA devices with ultra-thin and narrow channels (about 10 nm) are seen as the ideal architecture for off-state current control of sub-10 nm gate lengths (Ernst et al., 2006). Meanwhile, the current density per surface of such a device is limited by the lithography pitch, which dictates the distance between nanowires. The